In general, a turbo code, a low-density parity-check code (LDPC), a repeat accumulate (RA) code, and the like have been proposed as an error correcting code which attains a transmission speed close to a Shannon limit in a practical process. Such error correcting codes are employed in communication standards. For example, the turbo code is employed in Long Term Evolution (LTE) which is one of the communication standards standardized by Third Generation Partnership Project (3GPP) (refer to 3GPP TS 36.212 v.8.0.0, for example).
FIG. 1 is a diagram schematically illustrating a configuration of a turbo encoding device in the related art. A turbo encoding device 100 includes two encoders 101 and 102, an interleaver 103, and a multiplexer 104. An information bit string to be encoded is supplied to the encoder 101, the interleaver 103, and the multiplexer 104 in a unit of a predetermined bit length.
The encoder 101 generates a first parity bit string by performing recursive convolutional encoding on the supplied information bit string, for example. The first parity bit string is supplied to the multiplexer 104. Meanwhile, the interleaver 103 performs sorting on the supplied information bit string in accordance with a predetermined rule. The information bit string sorted by the interleaver 103 is supplied to the encoder 102. As with the encoder 101, the encoder 102 generates a second parity bit string by performing recursive convolutional encoding on the supplied bit string. Thereafter, the second parity bit string is supplied to the multiplexer 104. The multiplexer 104 multiplexes the supplied information bit string having the predetermined bit length (hereinafter referred to as a “systematic bit string”) and the first and second parity bit strings with one another so as to obtain a single data block. Then the multiplexer 104 outputs the data block as a turbo code.
The turbo code, the LDPC code, and the RA code are decoded by recursively or repeatedly performing a decoding process using a decoding device. For example, the decoding device which decodes the turbo code includes a component decoder which repeatedly performs a decoding process on each predetermined amount of data (refer to Japanese Laid-open Patent Publication No. 2006-109272, for example). Japanese Laid-open Patent Publication No. 2006-109272, for example, discusses a turbo decoding device including two component decoders. One of the component decoders of the turbo decoding device calculates a first information likelihood in accordance with an information bit string and a first parity bit string which are extracted from a data block which has been subjected to turbo encoding and a first prior likelihood. On the other hand, the other component decoder obtains a second information likelihood in accordance with an information bit string obtained by interleaving the information bit string extracted from the data block, a second parity bit string which is extracted from the data block and a second prior likelihood. The first and second prior likelihoods are calculated in accordance with the second and first information likelihoods, respectively.